1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of performing highly tilted halo implantation processes on semiconductor devices such as transistors.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. Field effect transistors are typically either NFET devices or PFET devices. During the fabrication of complex integrated circuits, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, referred to as a channel region, disposed between the highly doped source/drain regions. The channel length of a MOS transistor is generally considered to be the lateral distance between the source/drain regions.
Ion implantation is a technique that is employed in many technical fields to implant dopant ions into a substrate so as to alter the characteristics of the substrate or of a specified portion thereof. The rapid development of advanced devices in the semiconductor industry is based on, among other things, the ability to generate highly complex dopant profiles within tiny regions of a semiconducting substrate by performing advanced implantation techniques through a masking layer. In the case of an illustrative transistor, ion implantation may be used to form various doped regions, such as halo implant regions, extension implant regions and deep source/drain implant regions, etc.
An illustrative ion implantation sequence for forming various implant regions for an illustrative prior art transistor 100 will now be discussed with reference to FIGS. 1A-1E. FIG. 1A depicts the transistor 100 at an early stage of fabrication, wherein a gate structure 14 has been formed above an illustrative bulk silicon substrate 10. An active region 13 is defined in the substrate 10 by a shallow trench isolation structure 11. The gate structure 14 typically includes a gate insulation layer 14A, e.g., silicon dioxide, a conductive gate electrode 14B, e.g., polysilicon, and a gate cap layer 14C, e.g., silicon nitride. The gate structure 14 may be formed by forming layers of material that correspond to the gate insulation layer, the gate electrode and the gate cap layer and thereafter patterning those layers of material using known etching and photolithography techniques.
The masking layers that would be used during the implantation sequence shown in FIGS. 1A-1E are not depicted in the drawings. As shown in FIG. 1B, an angled ion implantation process 15 is performed to form so-called halo implant regions 15A in the substrate 10. The purpose of the halo implant regions 15A is to reinforce the doping of the substrate. For an NFET device, the halo implant regions 15A are comprised of a P-type dopant material, whereas, for a PFET device, the halo implant regions 15A are comprised of an N-type dopant material. The ion implant process 15 is performed at an angle 17 (relative to the vertical) which may vary between about 20-30 degrees.
Next, as shown in FIG. 1C, an ion implantation process 20 is typically performed to form so-called extension implant regions 20A in the substrate 10. Typically, the extension implant regions 20A will be self-aligned with respect to the sidewall of the gate structure 14 (for NFET devices) or there may be an offset spacer or liner (not shown) formed on the sidewall of the gate structure 14 prior to performing the extension implant process 20 (for a PFET device). For an NFET device, the extension implant regions 20A are comprised of an N-type dopant material, whereas, for a PFET device, the extension implant regions 20A are comprised of a P-type dopant material.
Then, as shown in FIG. 1D, sidewall spacers 16 are formed proximate the gate structure 14. The sidewall spacers 16 are typically formed by conformably depositing a layer of spacer material and thereafter performing an anisotropic etching process. With continuing reference to FIG. 1D, an ion implantation process 22 is performed on the transistor 100 to form so-called deep source/drain implant regions 22A in the substrate 10. The ion implantation process 22 performed to form the deep source/drain implant regions 22A is typically performed using a higher dopant dose and a higher implant energy than the ion implantation process 20 that is performed to form the extension implant regions 20A. For an NFET device, the source/drain implant regions 22A are comprised of an N-type dopant material, whereas, for a PFET device, the source/drain implant regions 22A are comprised of a P-type dopant material.
Thereafter, as shown in FIG. 1E, a heating or anneal process is performed to form the final source/drain regions 24 for the transistor 100. This heating process repairs the damage to the lattice structure of the substrate material as a result of the implantation processes and it activates the implanted dopant materials, i.e., the implanted dopant materials are incorporated into the silicon lattice. The various implantation processes described above may be performed using well-known ion implantation systems. Of course, the implant sequence described above may be varied. For example, the halo implant regions 15A may be formed after the extension implant regions 20A if desired.
FIGS. 1F and 1G will be referenced to describe various limitations as it relates to the formation of halo implant regions for semiconductor devices, such as transistors. As depicted therein, a plurality of gate structures 14 are formed above a substrate 10. In modern semiconductor devices, the gate structures 14 are very small and have a very small distance or pitch between adjacent gate structures 14. For example, in one illustrative embodiment, the gate structures 14 may have an overall height 25 of about 100-110 nm, a width (or critical dimension) 23 of about 30-40 nm, and they may have a spacing 27 between them of about 120 nm or so. The gate electrode 14B may have a height 25A of about 50-60 nm and the gate cap layer 14C may have a thickness 25B of about 40-50 nm.
FIG. 1F depicts the situation where a halo implant process is performed on the devices at a relatively low implant angle (relative to the vertical), e.g., about 20-30 degrees, like the illustrative angled implant process 15 described above and depicted in FIG. 1F. At relatively low implant angles, there is sufficient room between adjacent gate structures 14 such that a sufficient number of ions are not blocked by the gate structures 14 and ions may be implanted to form the halo implant regions discussed above. FIG. 1G depicts a situation where a relatively high-angled halo implant process 30, e.g., a process performed at an implant angle 31 of about 35-50 degrees or more (relative to the vertical). In such a highly angled implant process 30, the gate structures 14 effectively block the ions from being implanted into the substrate 10. Accordingly, such highly tilted halo implant processes may not be used even though the use of such highly angled halo implantation processes may be desirable or needed.
FIG. 2 depicts another situation where the formation of halo implant regions involves rotation of the wafer. In many product designs, the long axis of the gate electrodes of the various transistors are all parallel to one another—these may be generically referred to as “standard” or “vertical” transistors. Frequently, the long axis of the gate electrodes of such standard transistors is positioned parallel to a notch in a semiconducting substrate, wherein the notch indicates a particular crystallographic orientation. However, in other product applications, the product may contain both standard transistors and so-called “horizontal” transistors, wherein the long axis of the horizontal transistor is positioned at an angle of about 90 degrees relative to the long axis of the standard transistors. Various input/output devices are one example where such horizontal transistors may be found. FIG. 2 depicts an illustrative standard transistor 40 and a horizontal transistor 50. The standard transistor 40 comprises a gate electrode 40G, a source region 40S and a drain region 40D. The horizontal transistor 50 comprises a gate electrode 50G, a source region 50S and a drain region 50D.
The long axis 40A of the standard transistor 40 is positioned approximately parallel to the schematically depicted wafer notch 60. The long axis 50A of the horizontal transistor 50 is oriented at approximately 90 degrees relative to the long axis 40A of the standard transistor 40. The transistors 40, 50 may both be PFET devices or they may both be NFET devices.
As shown in FIG. 2, a tilted halo implant process 40H is performed to form halo implant regions (not shown) in the transistor 40. However, since the transistor 50 is rotated about 90 degrees, the halo implant process 40H does not form the desired halo implant regions on the transistor 50. That is, the halo implant process 40H is performed in a direction that corresponds to the gate width of the transistor 50. To form the halo implant regions (not shown) for the transistor 50, the substrate is rotated about 90 degrees, and a second halo implant process 50H is performed. The implant step 50H is sometimes referred to as a “twist” implant process due to the need to rotate the substrate. The halo implantation process 50H does not form halo implant regions in the transistor 40 due to the position of the transistor 40 during the halo implantation process 50H. That is, the halo implant process 50H is performed in a direction that corresponds to the gate width of the transistor 40. The implant processes 40H, 50H are typically performed at a relatively small implant angle (relative to the vertical) of about 30 degrees.
Such a two-step halo implantation process to form halo implant regions where the transistors are oriented at an angle of about 90 degrees relative to one another limits what can be done to improve device performance. For example, the implantation parameters for the second halo implant process 50H may need to be varied as compared to such parameters used during the first halo implant process 40H so as to change various performance characteristics of the transistor 50, e.g., the implantation dose during the second halo implant process 50H may need to be increased to increase the threshold voltage of the transistor 50 and to reduce its drive current until such time as the transistor 50 meets pre-established performance criteria. However, increasing the dopant dose employed during the halo implant process 50H may adversely affect the performance characteristics of other devices formed above the substrate that are exposed to the halo implant process 50H. For example, an increase in the dopant dose employed in the halo implant process 50H may, undesirably, increase the capacitance of, for example, a large area diode (not shown). The inventors have discovered that desirable changes to drive current of the transistor 50 may be accomplished by performing the halo implant process 50H at a higher implant angle without adversely affecting the capacitance of the illustrative large area diode. Unfortunately, as noted above with respect to FIGS. 1F-1G, due to the size of the gate structures and the limited spacing between adjacent gate structures, the shadowing effect of the gate structures 14 effectively prevents the use of highly-tilted halo implant processes in many modern semiconductor devices.
Many integrated circuit products require the formation of PFET and NFET devices on a common substrate. As is well known to those skilled in the art, manufacturing each of the devices involves the use of techniques that may be common to both types of devices and some techniques that are unique to each type of device. In the end, a process flow must be established that permits the most effective and efficient manufacturing of such devices as possible, typically in as few process steps as possible. For example, in a situation that involves both standard and horizontally oriented PFET transistors and standard NFET transistors, an illustrative process flow may include the following: Initially, isolation structures, such as trench isolation structures are formed in a substrate to define active regions for the various devices. Thereafter, the NFET device regions are masked and a first tilted halo implant process is performed for the standard PFET transistor. Thereafter, a vertically oriented extension implant processes is performed to form extension implant regions for both the standard and horizontal PFET transistors. Next, the substrate is rotated about 90 degrees and a second tilted halo implant process is performed to form halo implant regions in the horizontal PFET transistor. Of course, the first angled halo implant process could have been performed on the horizontal PFET transistor if desired. The halo implantation processes performed on the PFET transistors may be performed at an angle of about 30 degrees (relative to the vertical). After this implant sequence, embedded silicon/germanium (SiGe) source/drain regions are form for both the standard and horizontal PFET transistors using etching and epitaxial deposition processes known to those skilled in the art. The SiGe source/drain regions are typically doped in situ, although dopants may be introduced into the SiGe source/drain regions via ion implantation if desired. Thereafter, the masking layer used to mask the NFET device regions is removed and the gate cap layers, like the gate cap layer 14C depicted in FIG. 1A, are removed from the gate structures of all of the PFET and NFET devices. Next, the PFET device regions are masked and a tilted halo implant process is performed to form halo implant regions for the standard NFET devices. The halo implantation processes performed on the NFET transistors may be performed at a greater angle than the halo implantation processes performed on the PFET transistors, e.g., the halo implantation processes performed on the NFET transistors may be performed at an angle of about 35 degrees (relative to the vertical). Thereafter, a plurality of vertical ion implantation processes are performed to form extension implant regions and source/drain implant regions in the exposed NFET devices. An anneal process is then performed to activate the implanted dopant materials and to repair damage to the substrate due to the various ion implantation processes disclosed above. After the anneal process, conductive contacts are formed to the transistor devices using known techniques and so-called back-end-of-the-line (BEOL) processing is performed. Of course, as will be recognized by those skilled in the art, the above process flow does not describe each and every detailed step in the fabrication of such a semiconductor device, but it does set forth at least one illustrative process flow that has been employed as it relates to the formation of halo implant regions on integrated circuit products that include both standard and horizontal transistors.
The present disclosure is directed to various methods of performing highly tilted halo implantation processes on semiconductor devices, such as transistors, that may avoid, or at least reduce, the effects of one or more of the problems identified above.